1. Field of the Invention
The present invention relates to a semiconductor apparatus, and more particularly to a semiconductor random access memory in which bit lines are pre-charged to access to one of a plurality of memory cells and are discharged in a data outputting operation.
2. Description of Related Art
FIG. 6 is a circuit view showing a configuration of a conventional semiconductor random access memory.
As shown in FIG. 6, symbols Mmn (m=1,2,3, . . . ,M, and n=1,2,3, . . . ,N) denote a plurality of memory cells arranged in a matrix shape (M rows and N columns), and high level data (called "H" data) or low level data (called "L" data) is stored in each of the memory cells Mmn. Symbols BLn denote a plurality of bit lines arranged in parallel to each other in the columns in one-to-one correspondence. Each of the bit lines BLn is set to a high ("H") level in a pre-charge operation, and each bit line BLn is maintained to the "H" level or is changed to a low ("L") level in a reading operation and a writing operation. Symbols BLn' denote a plurality of bit lines arranged in parallel to each other in the columns in one-to-one correspondence so as to make one pair of bit lines BLn and BLn' for each column. Each of the bit lines BLn' is set to the "H" level in the pre-charge operation, and each of the bit lines BLn' is changed or maintained to the "L" or "H" level opposite to the level of the corresponding bit line BLn in the reading operation and the writing operation. Symbols WLm denote a plurality of word lines arranged in parallel to each other in the rows in one-to-one correspondence and crossing over the bit lines BLn and BLn'. Each of the word lines WLm transmits a row selection signal set to the "H" level in the reading operation and the writing operation. Symbols Tamn denote a plurality of first n-channel transistors (functioning as first transistors) in which each gate electrode is connected to the corresponding word line WLm. Each of the first n-channel transistors Tamn connects electrically the bit line BLn with a first side of the memory cell Mmn to equalize the electric level of the bit line BLn with that of the first side of the memory cell Mmn in cases where the row selection signal transmitting through the corresponding word line WLm is input to the gate electrode. Tbmn denotes a plurality of second n-channel transistors (functioning as second transistors) in which each gate electrode is connected to the corresponding word line WLm. Each of the second n-channel transistors Tbmn connects electrically the bit line BLn' with a second side of the memory cell Mmn to equalize the electric level of the bit line BLn' with that of the second side of the memory cell Mmn in cases where the row selection signal transmitting through the corresponding word line WLm is input to the gate electrode. A reference numeral 6 denotes a pre-charge control signal line. The pre-charge control signal line 6 transmits a pre-charge control signal indicating a time-period of the pre-charge operation for each cycle.
Symbols PRn denote a plurality of pre-charge circuits. Each of the pre-charge circuits PRn pre-charges the corresponding pair of bit lines BLn and BLn' during the time-period of the pre-charge operation indicated by the pre-charge control signal transmitting through the pre-charge control signal line 6 to set the electric levels of the bit lines BLn and BLn' to the "H" level.
A reference numeral 7 denotes an address latch. The address latch 7 receives an address signal, which indicates an address (i,j) of a particular memory cell Mij to be accessed, from a central processing unit (not shown) or the like a-nd holds address data indicating a particular row and a particular column as the address (i,j) of the particular memory cell Mij. A reference numeral 8 denotes a row decoder. The row decoder 8 decodes the address data of the particular memory cell Mij held in the address latch 7 to specify the particular row and to heighten the electric level of a particular word line Wi corresponding to the particular row of the particular memory cell Mij to the "H" level in the reading operation. The first n-channel transistor Taij and the second n-channel transistor Tbij corresponding to the particular memory cell Mij are turned on, and the electric levels of a particular pair of bit lines BLj and BLj' are equalized with those of the sides of the particular memory cell Mij.
A reference numeral 9 denotes a column selector. The column selector 9 selects the particular pair of bit lines BLj and BLj' according to the address data held in the address latch 7. A reference numeral 10 denotes a sense amplifier. The sense amplifier 10 detects a pair of electric levels of the particular pair of bit lines BLj and BLj' selected in the column selector 9. A reference numeral 11 denotes an output control circuit. The output control circuit 11 performs an output control for the pair of electric levels of the particular pair of bit lines BLj and BLj' detected in the sense amplifier 10. A reference numeral 12 denotes a data bus. The data bus 12 transmits the pair of electric levels, which are output-controlled in the output control circuit 11 and indicate the "H" data or the "L" data stored in the particular memory cell Mij, to an external apparatus. FIG. 7 is a circuit view showing a configuration of each memory cell Mmn.
Each memory cell Mmn is a latch circuit which is composed of a pair of inverters directed to different directions in parallel to each other to set electric levels of the first and second sides of the memory cell Mmn to different levels. In cases where the "H" data (or the "L" data) is stored in the memory cell Mmn, the first side of the memory cell Mmn facing on the bit line BLn is set to the "H" level (or "L" level), and the second side of the memory cell Mmn facing on the bit line BLn' is set to the "L" level (or "H" level).
In the above configuration, an operation of the conventional SRAM is described with reference to FIG. 8.
FIG. 8 shows the relationship of electric levels ("H" and "L" levels) of a plurality of signals and lines of the conventional SRAM.
In this operation, the "H" data stored in the memory cell M11, the "L" data stored in the memory cell M21and the "H" data stored in the memory cell M12are, for example, read out in that order.
As shown in FIG. 8, the "H" data of the memory cell M11is read out in a first cycle, the "L" data of the memory cell M21is read out in a second cycle, and the "H" data of the memory cellM12 is readout inathird cycle. Indetail, a pre-charge operation is performed in the first half of the first cycle by using the pre-charge circuits PRn to set all bit lines BLn and BLn' to the "H" level. Thereafter, in the second half of the first cycle, address data, which indicates an address (1,1) of the memory cell M11and is held in the address latch 7, is decoded in the row decoder 8, the word line WL1 corresponding to the memory cell M11is selected according to the decoded data, and the word line WL1 is set to the "H" level by the row decoder 8 to 15 transmit a row selection signal to the memory cells M1n. Therefore, the gate electrodes of the first n-channel transistor Ta11and the second n-channel transistor Tb11are set to the "H" level according to the row selection signal, the first n-channel transistor Ta11and the second n-channel transistor Tb11are turned on, the first side of the memory cell M11set to the "H" level is electrically connected with the bit line BL1, the second side of the memory cell M11set to the "L" level is electrically connected with the bit line BL1', and the bit line BL1 is maintained to the "H" level because the electric level of the bit line BL1 is the same as that of the first side of the memory cell M11. In contrast, because the electric level of the bit line BL1' is higher than that of the second side of the memory cell M11, a charge of the bit line BL1' is discharged to the second side of the memory cell M11, so that the electric level of the bit line BL1' is changed to the "L" level. Thereafter, the pair of bit lines BL1 and BL1' electrically connected with the memory cell M11are selected by the column selector 9 according to the address data held in the address latch 7, and the pair of bit lines BL1 and BL1' are connected with the sense amplifier 10. In the sense amplifier 10, an electric potential difference between the selected bit lines BL1 and BL1' is detected and amplified, a particular electric level (for example, the "H" level) corresponding to the "H" data stored in the memory cell M11is produced according to the electric potential difference between the selected bit lines BL1 and BL1' and is output to the data bus 12 through the output control circuit 11. Therefore, the "H" data stored in the memory cell M11can be read out to an outer apparatus.
In the second cycle, the pre-charge operation is again performed in the first half of the second cycle to set all bit lines BLn and BLn to the "H" level. That is, the bit line BL1' changed to the "L" level in the second half of the first cycle is charged. Thereafter, in the second half of the second cycle, the word line WL2 corresponding to the memory cell M21is set to the "H" level by the row decoder 8 according to address data indicating an address (2,1), and the first n-channel transistor Ta21and the second n-channel transistor Tb21are turned on. Therefore, because the "L" data is stored in the memory cell M21, a charge of the bit line BL1 is discharged to the first side of the memory cell M21, and the electric level of the bit line BL1 is lowered to the "L" level. In contrast, the bit line BL1' is maintained to the "H" level. Thereafter, the pair of bit lines BL1 and BL1' electrically connected with the memory cell M21are selected by the column selector 9 according to the address data, the pair of bit lines BL1 and BL1' are connected with the sense amplifier 10 to detect an electric potential difference between the selected bit lines BL1 and BL1', a particular electric level (for example, the "L" level) corresponding to the "L" data stored in the memory cell M21is produced according to the electric potential difference and is output to the data bus 12 through the output control circuit 11. Therefore, the "L" data stored in the memory cell M21can be read out to the outer apparatus.
In the third cycle, the pre-charge operation is again performed in the first half of the third cycle to set all bit lines BLn and BLn' to the "H" level. That is, the bit line BL1 changed to the "L" level in the second half of the second cycle is charged. Thereafter, in the second half of the third cycle, the word line WL1 corresponding to the memory cell M12is set to the "H" level by the row decoder 8 according to address data indicating an address (1,2), and the first n-channel transistor Ta12and the second n-channel transistor Tb12are turned on. Therefore, because the "H" data is stored in the memory cell M21, the bit line BL2 is maintained to the "H" level, and the electric level of the bit line BL2' is lowered to the "L" level. Thereafter, the pair of bit lines BL2 and BL2' electrically connected with the memory cell M12are selected by the column selector 9 according to the address data, the pair of bit lines BL2 and BL2' are connected with the sense amplifier 10 to detect an electric potential difference between the selected bit lines BL2 and BL2', a particular electric level (for example, the "H" level) corresponding to the "H" data stored in the memory cell M12is produced according to the electric potential difference and is output to the data bus 12 through the output control circuit 11. Therefore, the "H" data stored in the memory cell M12can be read out to the outer apparatus.
However, because the "H" data or the "L" data is stored in each of all the memory cells Mmn, the electric level of one bit line of each pair of bit lines BLn and BLn' is necessarily lowered to the "L" level each time the reading operation for one memory cell Mmn is performed after the pre-charge operation. Therefore, in addition to the charging for one bit line of one pair of bit lines BLj and BLj' corresponding to one particular memory cell Mij to be accessed, a charging for the pairs of bit lines BLn and BLn' except for the pair of bit lines BLj and BLj' is required for each pre-charge operation. For example, in the second half of the first cycle, because the second n-channel transistor Tb12are also turned on by the "H" level signal of the word line WL1 to equalize the electric level of the bit line BL2' with the second side of the memory cell M12storing the "H" data, the electric level of the bit line BL2' is lowered to the "L" level as well as that of the bit line BL1', so that it is required in the first half of the second cycle to charge the bit line BL2' in addition to the bit line BL1'. Also, in the same manner, it is required in the first half of a fourth cycle following the third cycle to charge the bit line BL1' in addition to the bit line BL2'.
Particularly, in cases where the number of memory cells is enormously increased because a memory capacity required for the SRAM is increased, there is a probability that an excessive current transmits through the conventional SRAM. Therefore, there are many drawbacks such as the increase of a consumed electric power, the increase of a heat generation, no stabilization in an electric power source, the occurrence of noises and the like.